The invention relates to the field of integrated circuits (IC) and semiconductor devices. In particular, the invention relates to wire bonding of copper interconnects when integrating microelectronic circuits with semiconductor devices.
Packaging is a basic process in semiconductor manufacturing. Packaging of electronic circuits provides interconnections and a suitable operating environment for predominantly electrical circuits to process or store information. Electronic packages contain many electrical circuit components, e.g., resistors, capacitors, diodes and transistors. In order to form circuits, these components require interconnections.
As information systems store and process large amounts of information, a large number of circuits and interconnections is needed. In meeting that need, chips are interconnected onto plastic, ceramic or coated-metal first-level packages. The electrical connections between chip and package, referred to as chip-level interconnections, are commonly performed using various chip bonding technologies, such as wire bonding and flip-chip technologies. The choice of chip bonding technology depends on the number and spacing of input/output (I/O) connections on the chip and the substrate, interconnect material selection, as well as permissible cost.
In wire bonding, very fine wires are attached to semiconductor components in order to interconnect these components with each other or with package leads. Its widespread use is primarily based on the fact that a large number or density of chip connections can be achieved with this technology, while at the same time providing a low cost per connection. Use of wire bonding is generally limited to chip bonding aluminum-based interconnect materials.
Flip-chip technology is often utilized over wire bonding for increased input/output (I/O) efficiency and greater speed in the IC since interconnect delays are minimized. In flip-chip bonding, a leadless, monolithic structure contains circuit elements designed to electrically and mechanically interconnect to a circuit by means of an appropriate number of bumps located on the face of a chip, which are covered by a conductive bonding agent.
Conventional designs utilize aluminum (Al) or aluminum alloys as the basic interconnect material for bonding pads in chip bonding. There is a trend in the art, however, to migrate from aluminum-based interconnect materials to other substances such as Copper (Cu). Copper, with its low resistivity, is an excellent material for the ever smaller wires in integrated circuits and provides better circuit performance and device reliability. Copper, nevertheless, has properties that are detrimental to semiconductor devices because it readily oxidizes in air at typical operating temperatures. Copper is also highly corrosive and contaminates semiconductor devices quickly if it is not isolated from other materials in the semiconductor. Due to these chemically active properties of copper, it is not feasible to utilize wire bonding when chip bonding copper interconnect materials. Consequently, the convention in the art is to utilize the flip-chip method to chip bond copper interconnects.
FIG. 1 illustrates a conventional flip-chip bonding process. The conventional flip-chip bonding process is described in Microelectronics Packaging Handbook, Rao R. Tummala and Eugene J. Rymaszewski (eds.), Van Nostrand Reinhold, New York (1989), pages 366-382. Referring to FIG. 1, flip-chip bonding utilizes solder bumps 12 deposited on wettable metal terminals on a Chip 14 and a matching array or arrangement of solder wettable terminals 16 on Substrate 18. Chip 14, which is upside-down, is aligned with Substrate 18, and solder joints formed by solder bumps 12 and metal terminals 16 are made simultaneously by heating and reflowing solder bumps 12.
Flip-chip technology is more expensive than wire bonding and requires a higher capital cost in process equipment. Moreover, compared with wire bonding, flip-chip technology requires additional process steps. For example, flip-chip bonding requires an underbump metallization structure that has to be deposited and patterned prior to the formation of the solder bumps. The underbump metallurgy often contains three or more complex metallization layers that must be deposited and patterned. The additional deposition processes result in increased cost in manufacturing the semiconductor device, often requiring additional assembly work performed in-house or by outside contractors. Moreover, the patterning processes require complex lithographic and etching process steps that add to the manufacturing cost. Furthermore, complex processes are necessary for the fabrication of the solder bumps which require solder deposition, patterning and reflow process steps.
Therefore, what is needed in the art is an optimized method of manufacturing semiconductor devices with copper interconnects, and more particularly, a method that is more cost efficient than flip-chip technology but uses manufacturing equipment commonly available in the art (such as equipment conventionally available in wire bonding).
The present invention uses wire bonding technology to bond interconnect materials that oxidize easily by using a wire with stable oxidation qualities. A passivation layer is formed on the semiconductor substrate to encapsulate the bonding pad made from the interconnect material such that the wire bonds with the passivation layer itself, not with the interconnect material. The passivation layer is selected to be a material that is metallurgically stable when bonded to the interconnect material. Since the wire is stable compared with the interconnect material, i.e., it does not readily corrode, a reliable mechanical and electrical connection is provided between the semiconductor device (interconnect material) and the wire, with the passivation layer disposed therebetween.
The invention is economically advantageous that it utilizes a relatively low-cost wire bonding technology, which does not require additional equipment and capital investment. In addition, the invention efficiently completes the chip bonding process without requiring extra metallization steps.